1. Field of the Invention
The present invention relates to a chip size stack package and a method of fabricating the chip size stack package, and more particularly, the present invention relates to a stack package in which at least two semiconductor chips are stacked to accomplish a size substantially corresponding to that of the conventional semiconductor chip, and a method of fabricating the chip size stack package.
2. Description of the Related Art
Nowadays, the increase in a capacity of a memory chip is undergoing rapid progress. In this regard, while a 128 M DRAM is currently produced in large quantities, a 256 M DRAM will instead be mass-produced in the near future.
As a method for increasing a capacity of a memory chip, i.e., for rendering a high integration rate, a technique of inserting more cells into a preset area of a semiconductor device, is disclosed in the art. However, it takes a lengthy period of time to develop such technique, and the technique requires a high precision with respect to forming a line width, etc. To cope with these problems, recently, a stacking technique which enables a high integration rate to be realized in a simpler manner, has been vigorously developed.
The term, xe2x80x9cstackingxe2x80x9d which is used in the semiconductor industry, means a method of doubling a capacity of a memory chip by heaping up at least two semiconductor chips in a vertical direction. By the stacking technique, for instance, a 128 M DRAM device can be constituted by two 64 M DRAM devices and a 256 M DRAM device can be constituted by two 128 M DRAM devices.
In a typical example of stack packages which are produced using the stacking technique, inner leads of a lead frame are attached, using an adhesive, to a semiconductor chip on an upper surface of which bond pads are located. The inner leads are connected to the bond pads through metal wires. The entire structure is molded by an encapsulate in a manner such that outer leads of the lead frame are exposed at sides of the semiconductor chip.
On the package constructed as just mentioned above, there is stacked another package having the same construction. In other words, outer leads of the upward positioned package are coupled to a middle portion of the lead frame of the downward positioned package, whereby an electrical connection between two packages is effected.
However, the stack package according to the conventional art suffers from defects in that a thickness of the entire stack package is increased. Moreover, since a signal must be transmitted from the outer leads of the upper package through the lead frame of the lower package, a signal transmitting path is overly lengthened. Furthermore, due to the fact that the leads of the upper and lower packages are coupled to each other by means of soldering, an inferior connection may result from an improper soldering.
To solve these defects, another conventional stack package as shown in FIG. 1 is disclosed in the art. As shown in FIG. 1, upper and lower semiconductor chips 1a and 1b having surfaces on which bond pads are formed, are arranged in a manner such that the surfaces thereof are opposed to each other at a predetermined interval. Upper and lower lead frames 2a and 2b are bonded to the respective surfaces of the upper and lower semiconductor chips 1a and 1b on which surfaces the bond pads are formed, and inner leads of the upper and lower lead frames 2a and 2b are electrically connected to the bond pads by metal wires 3. On the other hand, an outer end of the upper lead frame 2a is bonded to a middle portion of the lower lead frame 2b. The resultant structure is molded by an encapsulate 4 in a manner such that only outer leads of the lower lead frame 2b are exposed.
Nevertheless, the conventional stack package as shown in FIG. 1 still encounters drawbacks as described below.
First, while a signal transmitting path is shortened, if a flaw is caused in one semiconductor chip, two semiconductor chips should be discarded together.
Moreover, by the fact that the respective lead frames are located in such a way as to be opposed to each other, a defective proportion can be increased due to a tolerance between the two lead frames. Also, because the two lead frames are joined to each other using a laser, costly laser equipment is needed. Particularly, since the lead frames are semi-permanently joined to each other, a repairing operation afterwards may be impossible. Further, in the case that a size of a memory chip varies, a lead frame must be newly manufactured.
In addition, because the respective semiconductor chips are completely molded by the encapsulate, heat dissipation cannot be effectively executed while the upper and lower semiconductor chips are driven. That is to say, since a heat sink cannot be adequately installed, heat dissipation cannot be implemented in a sufficient degree.
Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide a chip size stack package which prevents signal interference from being generated and shortens a signal transmitting path, while not increasing an entire thickness, and a method of fabricating the chip size stack package.
Another object of the present invention is to provide a chip size stack package in which an electrical signal connection between stacked semiconductor chips is realized through a simple process without using costly laser equipment, and a method of fabricating the chip size stack package.
Still another object of the present invention is to provide a chip size stack package in which respective semiconductor chips are coupled with each other in such a way as to be capable of being easily detached from each other, whereby it is possible to prevent the chip size stack package from being discarded as a whole when a flaw is induced in one semiconductor chip, and a method of fabricating the chip size stack package.
Yet still another object of the present invention is to provide a chip size stack package which enables a heat sink to be attached to a board, whereby a heat dissipation characteristic is improved, and a method of fabricating the chip size stack package.
In order to achieve the above objects, a chip size stack package according to the present invention is constructed as described below.
Two semiconductor chips are arranged in a manner such that their bond pads-forming surfaces are opposed to each other. Insulating layers are applied to the bond pads-forming surfaces of the semiconductor chips, and via-holes for exposing bond pads are formed in the insulating layers. Metal traces which are exposed at both sides of the insulating layers are formed on the via-holes, whereby the insulating layers are bonded to each other and the metal traces are also bonded to each other. One ends of metal wires are connected to the metal traces which are exposed at the insulating layers, and both sides of the semiconductor chips are molded by an encapsulate in a manner such that the other ends of the metal wires are exposed.
On the other hand, instead of the metal wires, pattern tapes can be used. One ends of the pattern tapes are electrically connected to the metal traces at the same time when the insulating layers are bonded to each other, and the other ends of the pattern tapes are exposed. In this case, a space between the staked semiconductor chips is also molded. In place of the encapsulate, an anisotrophic conductive adhesive (ACA) can be intervened between the semiconductor chips. In the above-described three structures, it is preferred that a heat sink be attached to a surface of the upper semiconductor chip.
The chip size stack package constructed as mentioned above is fabricated as stated below.
After an insulating layer is applied to a surface of a wafer which has a plurality of semiconductor chips, by etching the insulating layer, bond pads of each semiconductor chip are exposed. Metal traces which are connected to bond pads, are formed on the insulating layer. Then, by cutting the wafer along a scribe line, the wafer is divided into respective semiconductor chips. Thereafter, insulating layers of two semiconductor chips are thermally compressed, whereby respective metal trace layers are electrically connected with each other. After one ends of outside connection terminals are electrically connected to the metal traces, both sides of the respective semiconductor chips are molded by an encapsulate in a manner such that only the other ends of the outside connection terminals are exposed.
In the case that the outside connection terminals comprise metal wires, first, in a state wherein respective insulating layers are bonded to each other, one ends of the metal wires are bonded to portions of the metal traces which portions are exposed at sides of the insulating layers. In the case that the outside connection terminals comprise pattern tapes, one ends of the pattern tapes are bonded using an adhesive between the metal traces, a space between the respective semiconductor chips and both sides of the semiconductor chips are molded using an encapsulate. Before performing the molding process, an ACA can be intervened between the respective semiconductor chips. On the other hand, a heat sink can be attached to a surface of the upper semiconductor chip.
By the features of the present invention, since metal traces are used instead of lead frames, signal interference is minimized. Due to the fact that the lead frames are not used, costly laser equipment for joining the lead frames are not needed. Moreover, by the fact that an encapsulate molds only sides of the stacked semiconductor chips, by removing the encapsulate at the sides of the stacked semiconductor chips, the stack semiconductor chips can be easily detached from each other. Further, as a surface of each semiconductor chip is exposed, it is possible to attach a heat sink to the surface.